Mr. Huan Kan Profile

Huan Kan

at Semiconductor Manufacturing International Corp

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Publications (3)

Proceedings Article | 20 March 2019 Paper

An efficient way of automatic layout decomposition and pattern classification

Zhenzhen Wan, Limei Liu, Huan Kan, Qijian Wan, Xinyi Hu, Zhengfang Liu, Chunshan Du

Proceedings Volume 10962, 1096214 (2019) https://doi.org/10.1117/12.2515137

KEYWORDS: Image classification, Library classification systems, Databases, Logic, Metals, Standards development, Front end of line, Back end of line, Design for manufacturing

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Proceedings Article | 20 March 2018 Paper

Using pattern based layout comparison for a quick analysis of design changes

Lucas Huang, Legender Yang, Huan Kan, Elain Zou, Qijian Wan, Chunshan Du, Xinyi Hu, Zhengfang Liu

Proceedings Volume 10588, 105880X (2018) https://doi.org/10.1117/12.2297346

KEYWORDS: Databases, Design for manufacturability, Manufacturing, Failure analysis, Data processing

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A design usually goes through several versions until achieving a most successful one. These changes between versions are not a complete substitution but a continual improvement, either fixing the known issues of its prior versions (engineering change order) or a more optimized design substitution of a portion of the design. On the manufacturing side, process engineers care more about the design pattern changes because any new pattern occurrence may be a killer of the yield. An effective and efficient way to narrow down the diagnosis scope appeals to the engineers. What is the best approach of comparing two layouts? A direct overlay of two layouts may not always work as even though most of the design instances will be kept in the layout from version to version, the actual placements may be different. An alternative way, pattern based layout comparison, comes to play. By expanding this application, it makes it possible to transfer the learning in one cycle to another and accelerate the process of failure analysis.

This paper presents a solution to compare two layouts by using Calibre DRC and Pattern Matching. The key step in this flow is layout decomposition. In theory, with a fixed pattern size, a layout can always be decomposed into limited number of patterns by moving the pattern center around the layout, the number is limited but may be huge if the layout is not processed smartly! A mathematical answer is not what we are looking for but an engineering solution is more desired. Layouts must be decomposed into patterns with physical meaning in a smart way. When a layout is decomposed and patterns are classified, a pattern library with unique patterns inside is created for that layout. After individual pattern libraries for each layout are created, run pattern comparison utility provided by Calibre Pattern Matching to compare the pattern libraries, unique patterns will come out for each layout. This paper illustrates this flow in details and demonstrates the advantage of combining Calibre DRC and Calibre Pattern Matching.

Proceedings Article | 20 March 2018 Paper

Leveraging pattern matching to solve SRAM verification challenges at advanced nodes

Huan Kan, Lucas Huang, Legender Yang, Elaine Zou, Qijian Wan, Chunshan Du, Xinyi Hu, Zhengfang Liu, Yu Zhu, Recoo Zhang, Elven Huang, Jonathan Muirhead

Proceedings Volume 10588, 105880Z (2018) https://doi.org/10.1117/12.2297340

KEYWORDS: Visualization, Multilayers, Manufacturing, Intellectual property

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