Local memory architecture plays an important role in high performance massively parallel vision chip. In this paper, we propose an enhanced memory architecture with compact circuit area designed in a full-custom flow. The memory consists of separate master-stage static latches and shared slave-stage dynamic latches. We use split transmission transistors on the input data path to enhance tolerance for charge sharing and to achieve random read/write capabilities. The memory is designed in a 0.18 μm CMOS process. The area overhead of the memory achieves 16.6 μm2/bit. Simulation results show that the maximum operating frequency reaches 410 MHz and the corresponding peak dynamic power consumption for a 64-bit memory unit is 190 μW under 1.8 V supply voltage.
In this paper we present a programmable computational image sensor for high-speed vision. This computational image
sensor contains four main blocks: an image pixel array, a massively parallel processing element (PE) array, a row
processor (RP) array and a RISC core. The pixel-parallel PE is responsible for transferring, storing and processing image
raw data in a SIMD fashion with its own programming language. The RPs are one dimensional array of simplified RISC
cores, it can carry out complex arithmetic and logic operations. The PE array and RP array can finish great amount of
computation with few instruction cycles and therefore satisfy the low- and middle-level high-speed image processing
requirement. The RISC core controls the whole system operation and finishes some high-level image processing
algorithms. We utilize a simplified AHB bus as the system bus to connect our major components. Programming
language and corresponding tool chain for this computational image sensor are also developed.
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