KEYWORDS: Etching, System on a chip, Process control, Factor analysis, Semiconductors, Tolerancing, Semiconducting wafers, Photoresist processing, Optical lithography, Plasma, Inspection
In recent year, the thermal effect has become a critical issue on the operation of memory cell. As heating time or temperature increases, the performances of memory cells are degraded due to its low thermal stabilities. Therefore, processes working at low temperature are necessary not to hurt the thermal stability. In this paper, we introduced LTSOC (Low Temperature Spin-On Carbon), which is believed to minimize the thermal loads because its cross-linker works at low temperature. Also, it would be important to fulfill the needs for the other properties of SOC like filling ability and etching resistance. So, we verified all these basic characteristics with proper resist and etching processes by getting good final pattern profile. As a result, LT-SOC is suggested for etching barrier without affecting on cell operation of memory devices.
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