Chemical mechanical polishing (CMP) is a critical process in Integrated Circuit (IC) manufacturing used to ensure planarity of the layers which comprise the IC. The IC design and CMP process must be optimally integrated otherwise dishing and erosion may occur on any of the various layers resulting in significant degradation impacting lithographic pattern fidelity and performance variability. Consequently, it is desirable to accurately predict if and where these hotspots (HS) will appear early in the design to ensure high manufacturing yield and predicted performance. In this work, we use a Deep Learning (DL) multilayer convolutional neural network (CNN) algorithm to model CMP hotspots for full-chip multilayer layouts. The DL model consists of convolutional layers for automatic feature extraction and fully-connected CNN layers for HS classification and detection. Our implementation can learn/capture effects that go beyond traditional methods in that these effects can be discovered from previous technologies with transfer learning and the model can be trained with either simulation or topography measurement data. Further, the model is trained from multiple layers and CMP results thereby enabling modeling and prediction of hotspots resulting from complex inter-layer interactions or effects which may escape traditional methods. With the proposed DL model, we achieved a hotspot prediction accuracy of up to 98% with up to 10 metal layers. After training the model, the inference time for a full chip can be up to 10x faster than existing CMP tools. This flow enables CMP/Fill-aware design validation that can help to create optimal high-yielding customer designs.
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