ASELSAN has made significant progress on developing its short-wave infrared (SWIR) technology, with a focus on improving dark current, quantum efficiency, and operability. In recent work, shunt current and generation-recombination current have been identified as the predominant dark current mechanisms. Shunt current can be suppressed by reducing the dangling bond count which requires optimizing the focal plane array passivation, and generation-recombination current can be reduced by improving the device design. Extensive work on process optimization employing various passivation schemes combined with theoretical layer design has lowered the SWIR focal plane array pixel dark current values down to < 1 nA/cm2. Furthermore, achieving low dark current without sacrificing high quantum efficiency (exceeding 80%), by building on the previous process and post-process work, has enhanced the sensor’s ability to capture faint signals. 640x512 format and 15 μm pitch SWIR focal plane arrays coupled with ASEL64015CG read-out circuits have consistently reached > 99.9% operability. After maturing the development work, ASELSAN launches its SWIR detector, LEOP-640/15-SW, pioneering the company’s photodetector production. In this paper, the results of the theoretical and experimental R and D work on LEOP photodetector development and production at ASELSAN are presented.
A 1280x1024 Readout Integrated Circuit (ROIC) with 15 μm pixel pitch for MWIR and LWIR applications is designed in 0.18 μm CMOS process. Integrate-Then-Read (ITR) and Integrate-While-Read (IWR) configurations are supported in snapshot mode. The ROIC pixel topology is direct injection (DI) with 3-bit programmable pixel gain. The minimum charge capacity is 0.8 Mé and the maximum full-well-capacity (FWC) is more than 13.2 Mé in ITR mode. 2, 4, 8, and 16 analog video output modes are also supported with a maximum frame rate of 240 fps at 16-output mode. A digital serial interface is used to program timing registers and analog biases. Integration time is programmable with 0.1 μs resolution up to 429 second using 10 MHz clock frequency. The pixel supports binning, windowing and anti-blooming functions. Digital and analog blocks of the ROIC operates using 1.8V and 3.3V supplies. The power consumption is less than 175 mW in 4-output mode of operation at 30 fps.
A 10μm pixel pitch 1280×1024 Readout Integrated Circuit (ROIC) for MWIR applications is designed and fabricated using 0.18 μm CMOS process. It operates in snapshot mode supporting both Integrate-Then-Read (ITR) and IntegratedWhile-Read (IWR) configurations. The ROIC pixel has direct injection (DI) input stage and provides 2-bit programmable pixel gain. It has a minimum charge capacity of 0.7 Mé and a maximum full-well-capacity (FWC) of more than 6.3 Mé in ITR mode. 4, 8 and 16 analog video output modes are also supported with a maximum frame rate of 120 fps at 16-output mode. All digital timing and analog biasing are programmable through a serial interface. Integration time is programmable with 0.1 μs resolution by internal timing circuitry. It supports binning, windowing and antiblooming functions. The ROIC operates with 3.3 V and 1.8 V supplies and dissipates less than 175 mW in 4-output mode of operation at 30 fps. An Analog-Front-End (AFE) card is designed to operate the ROIC and convert analog video outputs into 14-bit digital value. Digitized video data is further processed by 1-point and 2-point Non-Uniformity Correction (NUC), histogram equalization and bad pixel replacement algorithms. The ROIC has been tested with a prototype FPA at 77K. Measurement results of ASEL128010 indicate that it is functional at all operating modes including windowing and binning. The input referred noise level of the ROIC is 877 é at 6.3 Mé FWC.
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