New DFM tools appearing on the market hold a promise of assessing parametric and functional
yield loss due to lithography effects. The accuracy of underlying models can limit the veracity
of such assessment. For example, many lithography steps used in the fab are extremely nonlinear
and might exhibit significant differences from models used by the DFM tools.
Furthermore, inputs used in calibrating a model can limit its accuracy, and most organizations
are challenged to characterize the exact needs of a lithography model at a statistically relevant
sampling size. After discussing potential sources of inaccuracy in modeling, the paper will
describe a methodology for modeling and yield prediction based on such accurate modeling.
DFM tools have been all the rage in recent years. By exposing potential
manufacturability, timing and variation issues early, these tools can help the designers
correct such issues before the tape out. Such an early intervention delivers a faster
yield ramp for the product. For the lower volume devices, the faster yield ramp can help
meet the market window while for higher volume devices it can also mean millions of
dollars in cost savings. While there have been several DFM product announcements,
case studies focusing on actual usage of such tools are not publicly available.
In this article we share the data from a real customer evaluation and deployment. This
North American customer has deployed the tool and completed several TSMC 65nm
layouts.
By focusing on the motivation to use such a tool, the article will first quantify the
expected value from such a tool. Next the article will present the detailed evaluation
criteria for choosing a tool. Finally, actual error data from production tape outs and
performance metrics of the LCC tool will be presented showing runtime, scalability and
memory numbers.
Today, semiconductors are being connected to other components of the system through three main interconnect technologies - Wirebond, TAB and Solder bump. Of the three technologies, use of solder bump provides the lowest impedance electrical path and a high er I/O density as compared to wirebond and TAB. Wafer bumping is often accompanied by a need for redistribution of the current carrying pads on the silicon in order to reduce the substrate cost and better manufacturing yields, Besides, there is a need to deposit a metallic layer underneath the bump for good reliability of the packaged system. The two widely used processes used for depositing a thin metal film, either for redistribution or UBM are Physical Vapor Deposition and evaporation. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for going towards wafers level packaging solutions in order to minimize the packaging cost and giving high production rates.
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