A principal performance limitation of current computers is memory access latency. The random access time of DRAM can be as low as 20 ns but the overhead imposed by communication latency can increase the retrieval time to 150 ns in single processor systems or 1 ms in large multiprocessor systems. Optically interconnected VLSI offers the possibility of reductions in the communication component of memory latency of an order of magnitude. The improvement arises from the potential of direct high bandwidth low-latency links between any one chip and each one of a set of others. This potential principally arises from the ease of an optical implementation of fan-out and fan-in operations, together with the intrinsically high bandwidth of optical links. We have designed a scaleable system of processor-memory interconnections to explore this technology. Optical fan-out and fan-in modules will link a single processor to a bank of memory chips. The approach allows for multiple processors to be connected to multiple memory banks in an analogous fashion. The demonstrator will use 1-D VCSEL and photodiode arrays to provide optical i/o for the CPU and memory chips. The optical fan-out, fan-in and image relay can be implemented using an integrated planar optical system.
Andrew Walker, Stuart Fancey, M. Forbes, Gerald Buller, Mohammad Taghizadeh, Marc Desmulliez, Julian Dines, C. Stanley, G. Pennelli, Andrew Boyd, J. Pearson, Paul Horan, Declan Byrne, John Hegarty, Sven Eitel, Hans-Peter Gauggel, Karlheinz Gulden, A. Gauthier, P. Benabes, J. Gutzwiller, Michel Goetz
The physical limit on electronic data communication rates between silicon chips is projected to be of the order of Tbit/s over cm-scale connections. The semiconductor industry predicts that this level of i/o is likely to be required in the near future. Free-space optical connections to silicon VLSI are potentially able to offer much higher data-rates than electrical interconnects and are promising for future high-performance electronic systems. We have assembled the components of an optoelectronic 15 Gbit/s crossbar switch designed to include, internally, an optical data rate to a hybrid InGaAs/silicon chip in the Tbit/s regime. Input to the demonstrator is by an 8 X 8 VCSEL array operating at 250 Mbit/s channel, and these 64 channels are fanned out 8 X 8 times to give the high data rate onto the hybrid chip. This chip includes an array of 4096 InGaAs-based detectors flip chip bonded to silicon CMOS. The custom- designed CMOS performs packet routing under the control of an optical clock and the routed signals are output via differential modulator pairs, interlaced between the detectors on the InGaAs chip.
The increasingly high performance of electronic processors will place a burden on data communications in future systems. High speed and dense interconnections will be needed at various levels of a system hierarchy: among gates on a chip; among chips on a multi-chip module (MCM); among chips or MCMs on a board, and among boards via a backplane.
The optical components of a 64 X 64 optoelectronic crossbar interconnect are described. The specifications and performance of the bulk, micro-optic, diffractive and thin- film components are discussed.
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