This article reviews some of challenges that the Power MOSFET designers need to address to meet the ever growing
market demand for reducing power consumption in battery-powered portable applications. The critical power MOSFET
design parameters such as threshold voltage (Vth), drain-source breakdown voltage (BVdss), on-resistance (Rdson),
package footprint, gate-drive voltage, and Figure of Merit (FOM) have been discussed. It has been highlighted that the
scaling features and ultra-low on-resistance of the Trench Power MOSFETs can be advantageously utilized for powerloss
management. The MOSFET design requirements in battery protection circuits and load switches have been
presented. It has been emphasized that the Power MOSFET designers need to trade-off between on-resistance and
maximum current capability in smaller footprint packages. The merits of Wafer Level Chip Scale Package (WLCSP) in
achieving minimum foot print, ultra-low on-resistance, and improved thermal characteristics have been discussed.
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