Strategy for sub-80nm contact hole patterning considering device fabrication

Jin-Young Yoon; Mitsuhiro Hata; Jung-Hwan Hah; Hyun-Woo Kim; Sang-Gyun Woo; Han-Ku Cho; Woo-Sung Han

doi:10.1117/12.534811

14 May 2004 Strategy for sub-80-nm contact hole patterning considering device fabrication

Jin-Young Yoon, Mitsuhiro Hata, Jung-Hwan Hah, Hyun-Woo Kim, Sang-Gyun Woo, Han-Ku Cho, Woo-Sung Han

Proceedings Volume 5376, Advances in Resist Technology and Processing XXI; (2004) https://doi.org/10.1117/12.534811
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

As the required contact holes dimension (CD) reaches to the physical limit of the conventional lithography, the image quality formed in a photoresist film is degraded seriously. To overcome this obstacle, several process-based techniques for ArF lithography have been suggested and some of them are reported to show excellent feasibilities. In this article, three primary techniques for sub-80nm contact holes patterning are examined. They are ArF thermal flow, ArF SAFIER (Shrink Assist Film for Enhanced Resolution) and ArF RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink). These techniques are originated from different reaction mechanisms and result in distinguished shrink behaviors. Contact holes CDs of different patterns diverge one another depending on the adapted shrink process even though the initial CDs are identical. This is so called a bulk effect and is compensated by the optical proximity correction (OPC) procedure. The relationship of pattern CDs between mask and wafer is used to extract the correction factor. For the shrink process, it is divided to an optical factor and a process factor, that is, the shrink behavior is analyzed in terms of mask error factor (MEF) and process error factor (PEF). The PEF is calculated from the proportionality of post-shrink CD to initial CD of photoresist patterns. Using the PEF, it is possible to characterize each shrink process in the view of CD controllability. Consequently, we classify the shrink processes for the production of 65nm node devices considering the shrink properties and the cost of ownership.

Citation Download Citation

Jin-Young Yoon, Mitsuhiro Hata, Jung-Hwan Hah, Hyun-Woo Kim, Sang-Gyun Woo, Han-Ku Cho, and Woo-Sung Han "Strategy for sub-80-nm contact hole patterning considering device fabrication", Proc. SPIE 5376, Advances in Resist Technology and Processing XXI, (14 May 2004); https://doi.org/10.1117/12.534811

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