Background: As semiconductor technologies continue to shrink, optical proximity correction may not have enough space to optimize layout due to limitations from adjacent layers. Lithography friendly design (LFD) becomes a powerful tool to detect potential lithography yield killers for fabless side from 14-nm technology node and beyond. Design layout can be modified before tape-out to avoid future rework. However, huge runtime is the bottleneck of LFD.

Aim: Our paper puts forward an innovative layout decomposing algorithm to accelerate LFD at full-chip level.

Approach: The proposed projection-based high coverage fast (PBHCF) LFD layout decomposing algorithm partitions the full-chip layout as a set of unique patterns. The simulation runtime can be reduced by only simulating every unique pattern and corresponding optical interaction range in full chip. The LFD hotspots will be classified, analyzed, and repaired by pattern matching in batches for full-chip layout.

Results: The experiments compare hotspot accuracies and prediction speeds of proposed PBHCF LFD and the most commonly used accelerated algorithm, Smart LFD, for different layouts at chip level for metal 2 layer of 12-nm technology node with pure unidirectional routings. On one hand, the average accuracy of PBHCF LFD can achieve 97.07%, improving 3.4% than Smart LFD on average. On the other hand, PBHCF LFD improves the average prediction speed over regular LFD 19.51%. And the PBHCF LFD is faster than Smart LFD by 5.96%.

Conclusions: PBHCF LFD achieves higher accuracy and less runtime than Smart LFD. The verification experiments conducted on layouts at chip level show the feasibility of the proposed methodology.