Mr. Ahmed Mohyeldin Profile

Ahmed Mohyeldin

MTS CAD Design Engineer

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Publications (2)

Proceedings Article | 4 April 2018 Presentation + Paper

Litho friendly via insertion with in-design auto-fix flow using machine learning

Ahmed Mounir Elsemary, Moutaz Fakhry, Janam Bakshi, Nishant Shah, Mohamed Ismail, Fadi Batarseh, Uwe Paul Schroeder, Ahmed Mohyeldin, Jason Cain

Proceedings Volume 10588, 105880F (2018) https://doi.org/10.1117/12.2297499

KEYWORDS: Lithography, Metals, Optical lithography, Manufacturing, Machine learning, Image classification, Design for manufacturing, Library classification systems, Pattern recognition

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Proceedings Article | 3 April 2017 Presentation + Paper

Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs

Ahmed Mohyeldin, Uwe Paul Schroeder, Ramya Srinivasan, Haritez Narisetty, Shobhit Malik, Sriram Madhavan

Proceedings Volume 10148, 101480N (2017) https://doi.org/10.1117/12.2261588

KEYWORDS: Capacitance, Resistance, Metals, Design for manufacturing, Double patterning technology, Databases, Design for manufacturability, Manufacturing, Yield improvement, Photomasks

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In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes, the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method for providing the needed redundancy.

This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in this paper.

One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration.

The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint. Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical redundancy such that intolerable electrical impacts could be avoided.

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