The authors introduce initial simulation work on Photonic Bandgap Enhanced or PBE reticles that tends to address the manufacturing problems associated with typical PSM reticles while improving
potential resolution capabilities to 35 and 25 nm utilizing 193 nm immersion lithography. The proposed approach for manufacturing reduces the overall defect issues associated with PSM approaches.
As geometries shrink faster than the actual wavelength used for exposure, the Proximity influence distance, or PID of
nearest neighbor features starts to impact not only the overall RET of unit cells in the design library but also the
flattening of the hierarchy of the electronic design increasing the overall database size, computational times and
respective memory requirements per computational node.
In this paper we explore the impact of different PID values in relation to the overall flattening of hierarchy, time to
market and the impact on RET complexity as dimensions are shrunk in overall design.
E-Beam Lithography is still the driving technology for semiconductor manufacturing of critical levels at the 45nm node. Mask costs, yields and representation of the mask on wafer are important factors to consider. Mask-less E-beam lithography is being considered, but major manufacturing is still done by scanner technology. Therefore the same emphasis on modeling applied in the 1990's on the wafer is now being applied to mask technologies to drive down costs, improve yields and to develop viable mask to wafer transfer patterns.
Yield is ultimately connected to process latitude, which is limited by a variety of electron-material interaction issues. As in the optical world, the question is how to maximize the process window considering all the systematic and statistical error sources. Simulation can be used to find out the magnitude of yield limiting effects, and to evaluate the contributing error sources such as PEC file contributions. Film stacks are now becoming an important contributor to statistical error due to technologies such as tri-tone attenuated masks that place a thin layer of chrome over MoSi.
In this paper we will compare the SELID E-beam simulation to cross-sections of line-space and contact patterns. Demonstrations of simulation to real data and the use of simulation to further evaluate process window to enhance the learning mode during development cycles will be presented.
Data and discussions will be presented on the NTRM, National Technology Roadmap, for reticles based on a Process Integration perception. Specifically two layers are considered for this paper, the gate layer which is primarily a chrome geometry mask with a lot of open glass and a local interconnect layer which is primarily a chrome plate using clear geometries. Information from other sources is used where appropriate and actual in-house data is used to illustrate specific points. Realizing that demands from different customers for specific types of features tend to drive specific mask makers and their decisions on equipment purchases and processes. We attempt to help predict where Integration approaches have either caused a lag in technology pushes or have actually speeded up certain requirements. Discussions of integration requirements, which tend to push maskmakers, will be presented. Along with typical design approaches in OPC and PSM which either will push technology or actually slow down the trend towards smaller geometries. In addition, data will be presented showing how specific stepper characteristics may actually drive the customer's criteria, thus changing the requirements from customer to customer.
Bijnan Bandyopadhyay, Jon Cheek, Robert Dawson, Michael Duane, Jim Fulford, Mark Gardner, Fred Hause, Bernard Ho, Daniel Kadoch, Raymond Lee, Ming-Yin Hao, Chuck May, Mark Michael, Brad Moore, Deepak Nayak, John Nistler, Dirk Wristers
A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.
The use of I-Line exposure wavelength for manufacturing at and beyond 0.35 micrometers presents many challenges in manufacturing. The lack of resolution, depth of focus, exposure latitude, and iso/dense offsets have caused some to switch from I-Line to DUV. With our installed I-Line base we felt it necessary to implement techniques to extend our tool life, reduce manufacturing costs while improving manufacturing margins. The results of the differential modification techniques were used to reduce the effects of topography, density, and low k lens issues. The differences seen between the binary and phase shift plates show the advantage of phase shifting below 0.35 (mu) manufacturing. We have been able to demonstrate between critical dimension (CD) control using phase shift mask with dense iso compensation over a standard binary reticle. The data shows improved CD control across the stepper field, wafer, and overall lot distribution. The impact of this work was improved speed performance. It also allowed us to move the CD's to smaller dimension because of the better control without increasing fallout due to electrical parametric roll-off.
As the device performance requirements tighten to improve speed distributions, the speed binning caused by across the wafer critical dimension (CD) variation will have significant impact on manufacturing performance yields. Overall speed performance yields are impacted by wafer to wafer and across wafer poly CD and poly profile variation caused at photo and etch. With the use of our final technique, called `Exposure Compensation', we were able to compensate for CD variation seen at final FI CD and electrical test. Implementation of exposure compensation process gave an effective two week control that exceeded the goal of 90 nm total electrical distribution. The improved control at FI CD can clearly be seen from the results of electrical measurements and transistor performance. While the techniques adequately improve site to site variation, further work is still required to improve across field variation.
In this paper we present results of an algorithm that has been developed which is sensitive to phase defects of 60 degrees on i-line alternating PSMs. This algorithm consists of microcode and software which can be loaded into existing inspection hardware. The algorithm works in die-to-die inspection mode and uses both transmitted and reflected light images to maximize sensitivity. Isolated phase defects missing and misaligned shifter edges. A programmed phase defect test plate was developed to characterize defect detection sensitivity. Detection of 60 degree defects smaller than 0.75 micrometer has been demonstrated with this algorithm. Defect sensitivity characterization and actual production plate defect results are shown.
Increased lithographic performance has been the key enabler for the continued reduction of minimum device feature sizes down to 0.25 micrometers and beyond. However, this increase in performance has been accompanied by the added fabrication complexity of the various types of lithographic reticles. In addition to having submicrometer sized features, advanced optical masks are three dimensional in nature with high aspect ratio features of different materials in close proximity to each other. Lithographic process latitude, which determines the ultimate feasibility of that process, is critically dependent upon the level of measurement and control of these mask features. Standard reference materials are needed in order to improve the accuracy of the mask measurements, but do not yet exist. To initiate progress in this area, a set of test reticles has been fabricated to serve as in-house calibration standards and to study various phenomena affecting three-dimensional submicron dimensional metrology for advanced optical masks. The first member of the set, known as the Lateral Resolution Tester (LRT), contains chromium features on unetched quartz (opaque and partially transparent) having linewidths as narrow as 200 nm. The PSM Feature Tester contains many types of phase-shifting mask patterns with varying lateral dimensions. The Herschel Tester contains various phase-shifting apertures of different depths and widths. All of the patterns and concepts used in the set have been brought together in order to produce a new PSM metrology test/calibration mask known as the PSM Round Robin Reticle (RRR). The types of patterns as well as the techniques used to measure them are presented. The RRR will also be used as the test vehicle for a round robin comparison of measurements taken with metrology tools at different mask shops and to determine optimum designs for future PSM metrology calibration standards.
An aerial optical design rule checker (ODRC) that will handle large areas is used to validate the automatic CAD software used for application of alternating Phase Shift Mask technology to logic devices. An automatic alternating aperture layout algorithm developed internally by Advanced Micro Devices is applied to 0.24 to 0.50 micrometers electrical designs. The layout is then verified for different stepper and defocus values by the ODRC which utilizes the simulated aerial image to compare directly to the electrical design database. Entire databases are handled by fracturing the database into optically isolated areas or by using a sliding window technique. Small areas up to 420 um per side can be done with single processor workstations with at least 512 megabyte of memory. Larger problems require multiprocessor computers with at least 16 gigabyte of memory. Full circuit analysis should be done on systems with at least 64 gigabyte of memory in order to accomplish solving the problem in a reasonable time frame.
This paper describes a software program that compares the simulated aerial image of a mask pattern with the original, desired, mask pattern. The program uses the Fast Aerial Image Model (FAIM) to simulate the aerial image. A specific intensity contour is chosen and the distance from the contour to the desired design is calculated. Regions where the distance exceeds a specified tolerance are deemed failures and flagged. Corner-rounding errors are handled differently to line edge position errors. The threshold intensity used can be specified by the user, alternatively a `critical feature' may be defined and the threshold set to the intensity value required to print it on size. In addition to describing the program, we also show examples of how the aerial image contour predictions compare with simulations of resist profiles and actual printed resist images for the case of a SRAM cell.
Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys’ ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.
Issues associated with the commercialization of phase shift masks are discussed. Design layouts incorporating multiphase transitions and voting are presented along with methods of mask fabrication. Issues associated with mask inspection and repair are discussed, along with data on actual reticles produced using the prescribed method of manufacture. Cost of reticles in relation to potential wafer processing gains are compared along with problems associated with the increased complexity of the mask making process.
Phase-shifted patterns (alternating, 90-degree, and chromeless) have been incorporated into a reticle layout, fabricated with a MEBESR III system, and evaluated experimentally at 365 nm using steppers with numerical aperture (NA) ranging from 0.4 to 0.48 and partial coherence ranging from 0.38 to 0.62. Test circuit layouts simulate actual circuit designs with critical dimensions ranging from 0.2 micrometers to 1.2 micrometers . These results, combined with experimental measurement of layer to layer registration and aerial image simulations, provide a first-order assessment of e-beam lithography requirements to support phase-shift mask technology.
The three conventional techniques--optical, low voltage scanning electron microscopy (LVSEM), and electrical linewidth measurement--continue to be employed, but each technique has unique applications, problems, and limitations. In this paper these techniques are investigated for submicron linewidth metrology. A great deal of emphasis is placed on the calibration of these tools and the potential for problems associated with the tools.
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