The impact of bottom reflection on critical dimension (CD) processing window is intensively investigated with a
simulation using a full diffraction model (FDM) in which the effective reflectivity is calculated from standing wave
amplitude. Most importantly, the optical phase shift of the reflection is used as a design criterion and was found to be
the primary factor that affects the UV distribution, and, hence, has a strong impact on exposure latitude and depth of
focus. Foot exposure (FE) is introduced as a new metric to characterize the phase shift. Some single-layer and dual-layer
bottom anti-reflective coating (BARC) designs were implemented with an Exitech MS-193i immersion micro-stepper
(NA=1.3) for 45-nm dense lines at the Resist Test Center (RTC) at International SEMATECH, Albany, New
York. The experimental results show that FE is closely related to the CD processing window. In contrast to
conventional BARC usage, a small amount of substrate reflection with a controlled optical phase shift dramatically
improves CD processing window.
The 45-nm node will require the use of thinner photoresists, which necessitates the use of multilayer pattern transfer
schemes. One common multilayer approach is the use of a silicon-rich anti-reflective hardmask (Si BARC) with a
carbon-rich pattern transfer underlayer (spin-on carbon, or SOC). The combination of the two layers provides a highly
planar platform for a thin resist, and provides a route to etch substrates due to the alternating plasma etch selectivities of
the organic resist, inorganic Si BARC, and organic SOC. Yet such schemes will need to be optimized both for pattern
transfer and optics. Optimizing optics under hyper-NA immersion conditions is more complicated than with standard
(that is, NA<1) lithography. A rigorous calculation technique is used to evaluate and compare standard lithography to a
hyper-NA case using a multilayer stack. An example of such a stack is shown to have reasonable lithographic
performance.
This paper describes a new approach to help overcome the challenges of fabricating leading-edge devices by
using the trench first dual damascene process. Wet gap-fill materials are designed to reduce film thickness bias across a
wafer while keeping wafers in the same track in which they were coated. As the first process step, the wafer is coated
with a thick layer of wet gap-fill material to fill all trenches, thus guarding against resist pooling in the trenches. The
substrate is then baked to partially cure the wet gap-fill material. Standard 0.26N tetramethylammonium hydroxide
(TMAH) is then used to wet etch the wet gap-fill layer back to the substrate surface. For this study, substrates with
different trench depths and widths were processed, cross-sectioned, and measured. The effect of trench dimensions and
aspect ratio on the develop properties of WGF200-343 was investigated to see if it could be used as a wet trench-fill
material. This work will help develop a process that will allow the use of trench-first DD processing in modern
semiconductor manufacturing.
This paper discusses a novel approach of using a developer-soluble gap fill material, wherein the gap fill material is coated in a layer thick enough to planarize all the topography and is then recessed using a standard 0.26N TMAH developer. The material recess process takes place in the same coater track where it is coated and therefore simplifies the process and increases wafer throughput. Performance and properties of two types of developer-soluble gap fill materials (EXP03049 and NCA2528) based on two different polymer platforms will be discussed in detail.
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