Calibration pattern coverage is critical for achieving a high quality, computational lithographic model. An optimized calibration pattern set carries sufficient physics for tuning model parameters and controlling pattern redundancy as well as saving metrology costs. In addition, as advanced technology nodes require tighter full chip specifications and full contour prediction accuracy, pattern selection needs accommodate these and consider contour fidelity EP (Edge Placement) gauges beyond conventional test pattern sets and cutline gauge scopes. Here we demonstrate an innovative pattern selection workflow to support this industry trend. 1) It is capable of processing a massive candidate pattern set at the full chip level. 2) It considers physical signals from all of the candidate pattern contours. 3) It implements our unsupervised machine learning technology to process the massive amount of physical signals. 4) It offers our users flexibility for customization and tuning for different selection and layer needs. This new pattern selection solution, connected with ASML Brion’s MXP (Metrology of eXtreme Performance) contour fidelity gauges and superior, accurate Newron (deep learning) resist model, fulfills the advanced technology node demands for OPC modeling, thus offering full chip prediction power.
Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.
Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).
Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.
ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.
In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.
Sub-Resolution Assist Features (SRAF) are widely used for Process Window (PW) enhancement in computational
lithography. Rule-Based SRAF (RB-SRAF) methods work well with simple designs and regular repeated patterns, but
require a long development cycle involving Litho, OPC, and design-technology co-optimization (DTCO) engineers.
Furthermore, RB-SRAF is heuristics-based and there is no guarantee that SRAF placement is optimal for complex
patterns. In contrast, the Model-Based SRAF (MB-SRAF) technique to construct SRAFs using the guidance map is
sufficient to provide the required process window for the 32nm node and below. It provides an improved lithography
margin for full chip and removes the challenge of developing manually complex rules to assist 2D structures. The
machine learning assisted SRAF placement technique developed on the ASML Brion Tachyon platform allows us to
push the limits of MB-SRAF even further. A Deep Convolutional Neural Network (DCNN) is trained using a
Continuous Transmission Mask (CTM) that is fully optimized by the Tachyon inverse lithography engine. The neural
network generated SRAF guidance map is then used to assist full-chip SRAF placement. This is different from the
current full-chip MB-SRAF approach which utilizes a guidance map of mask sensitivity to improve the contrast of
optical image at the edge of lithography target patterns. We expect that machine learning assisted SRAF placement can
achieve a superior process window compared to the MB-SRAF method, with a full-chip affordable runtime significantly
faster than inverse lithography. We will describe the current status of machine learning assisted SRAF technique and
demonstrate its application on the full chip mask synthesis and how it can extend the computational lithography
roadmap.
Assist features are commonly used in DUV lithography to improve the lithographic process window of isolated features under illumination conditions that enable the printability of dense features. With the introduction of EUV lithography, the interaction between 13.5 nm light and the mask features generates strong mask 3D effects. On wafer, the mask 3D effects manifest as pitch-dependent best focus positions, pattern asymmetries and image contrast loss. To minimize the mask 3D effects, and enhance the lithographic process window, we explore by means of wafer print evaluation the use of assist features with different sizes and placements. The assist features are placed next to isolated features and two bar structures, consistent with theN5 (imec iN7) node dimensions for 0.33NA and we use different types of off-axis illumination . For the generic iN7 structures, wafer imaging will be compared to simulation results and an assessment of optimal assist feature configuration will be made. It is also essential to understand the potential benefit of using assist features and to weigh that benefit against the price of complexity associated with adding sub-resolution features on a production mask. To that end, we include an OPC study that compares a layout treated with assist features, to one without assist features, using full-chip complexity metrics like data size.
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