Mr. Yung-Feng Cheng Profile

Yung-Feng Cheng

Manager at United Microelectronics Corp

SPIE Involvement:

Author

Publications (24)

Proceedings Article | 26 May 2022 Poster + Paper

Poster + Paper

Using pattern analysis to improve wafer inspection flow

Hung-yu Lin, Ethan Wang, Jason Sweis, Philippe Hurat, Ya-Chieh Lai, Yu-Chin Pai, Ku Fang, Chin-Juan Li, Chia Wei Huang, Jun-Ming Chen, Yung-Feng Cheng

Proceedings Volume 12053, 120531T (2022) https://doi.org/10.1117/12.2613620

KEYWORDS: Inspection, Semiconducting wafers, Wafer inspection, Image classification, Yield improvement, Defect inspection, Data analysis, Software development, Defect detection, Tolerancing

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Proceedings Article | 26 September 2019 Paper

Paper

Practical lithography hotspot identification using mask process model

Pai Chi Chen, Chain Ting Huang, Shang Feng Weng, Yung Feng Cheng, Young Ham, Colbert Lu, Michael Green, Mohamed Ramadan, Hong Jen Lee, Chris Progler

Proceedings Volume 11148, 111481H (2019) https://doi.org/10.1117/12.2537935

KEYWORDS: Lithography, Photomasks, Process modeling, Optical proximity correction, Semiconducting wafers, Machine learning, Resolution enhancement technologies, Source mask optimization, Critical dimension metrology, Computer simulations

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Proceedings Article | 27 June 2019 Paper

Paper

Mask process correction for optical weak pattern improvement

Pai Chi Chen, Chain Ting Huang, Shang Feng Weng, Yung Feng Cheng, Kazunori Nagai, Kenji Kono

Proceedings Volume 11178, 111780Q (2019) https://doi.org/10.1117/12.2535770

KEYWORDS: Photomasks, Optical proximity correction, Scanning electron microscopy, Optical calibration, Critical dimension metrology, Optical simulations, Bridges, Etching, Calibration, Wafer-level optics

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Proceedings Article | 31 March 2014 Paper

Paper

Pattern environment impact on wafer of metal layers with high-NA process on advanced node

Chain Ting Huang, Yung Feng Cheng, Ming Jui Chen

Proceedings Volume 9052, 90522A (2014) https://doi.org/10.1117/12.2046195

KEYWORDS: Photomasks, Semiconducting wafers, Bridges, Optical proximity correction, Metals, Printing, Scattering, Error analysis, Double patterning technology, Photoresist materials

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Proceedings Article | 9 September 2013 Paper

Paper

In-die mask registration measurement on 28nm-node and beyond

Shen Hung Chen, Yung Feng Cheng, Ming Jui Chen

Proceedings Volume 8880, 88801O (2013) https://doi.org/10.1117/12.2025462

KEYWORDS: Image registration, Photomasks, Semiconducting wafers, Diffusion, Critical dimension metrology, Overlay metrology, Line width roughness, Lithography, Double patterning technology, Manganese

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Proceedings Article | 12 April 2013 Paper

Paper

Studies of a suitable mask error enhancement factor for 2D patterns

Chih I Wei, Yung Feng Cheng, Ming Jui Chen

Proceedings Volume 8683, 868324 (2013) https://doi.org/10.1117/12.2011509

KEYWORDS: Photomasks, Semiconducting wafers, Source mask optimization, Lithography, Critical dimension metrology, Printing, Metrology, Tolerancing, Wafer-level optics, Optical proximity correction

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Proceedings Article | 12 April 2013 Paper

Paper

The studies of SMO process on cont layer of 20nm node

Wei Cyuan Lo, Yung Feng Cheng, Ming Jui Chen

Proceedings Volume 8683, 86831Z (2013) https://doi.org/10.1117/12.2011345

KEYWORDS: Source mask optimization, Photomasks, Lithography, Process control, Resolution enhancement technologies, Logic, Extreme ultraviolet lithography, Radon, Manufacturing, Wafer-level optics

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Proceedings Article | 30 June 2012 Paper

Paper

EUV and 193 mask line width roughness (LWR) impact on wafer CD LWR

Chain Ting Huang, Cloud Cheng, Ming Jui Chen

Proceedings Volume 8441, 84410V (2012) https://doi.org/10.1117/12.964397

KEYWORDS: Line width roughness, Photomasks, Semiconducting wafers, Extreme ultraviolet, Printing, 3D modeling, Wafer-level optics, Line edge roughness, Scanning electron microscopy, Critical dimension metrology

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Proceedings Article | 13 March 2012 Paper

Paper

Studies of the source and mask optimization for 20nm node in the active layer

Chih-I Wei, Ruei-Hung Hsu, Yung-Feng Cheng, Ming-Jui Chen

Proceedings Volume 8326, 83262J (2012) https://doi.org/10.1117/12.917994

KEYWORDS: Source mask optimization, Photomasks, Semiconducting wafers, 3D modeling, Resolution enhancement technologies, Lithography, Scanning electron microscopy, Optical proximity correction, Molybdenum, Wafer-level optics

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Proceedings Article | 13 March 2012 Paper

Paper

Influence of SRAF size on main feature CD variation on advanced node

Wei Cyuan Lo, Yi Chou Chen, Yung Feng Cheng, Ming Jui Chen

Proceedings Volume 8326, 83262K (2012) https://doi.org/10.1117/12.917989

KEYWORDS: SRAF, Critical dimension metrology, Photomasks, Semiconducting wafers, Printing, Computer simulations, Lithography, Tolerancing, Diffractive optical elements, 3D modeling

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Proceedings Article | 14 October 2011 Paper

Paper

The influence and improvement of through pellicle image placement

Wei Cyuan Lo, Yung Feng Cheng, Ming Jui Chen, Katsuhiro Takushima, Shinichiroh Tashiro

Proceedings Volume 8166, 81663A (2011) https://doi.org/10.1117/12.900280

KEYWORDS: Pellicles, Photomasks, Semiconducting wafers, Adhesives, Image registration, Process control, Image processing, Reticles, Particles, Image analysis

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Proceedings Article | 4 March 2010 Paper

Paper

Wafer LMC accuracy improvement by adding mask model

Wei Cyuan Lo, Yung Feng Cheng, Ming Jui Chen, Peter Haung, Stephen Chang, Eiji Tsujimoto

Proceedings Volume 7640, 76402S (2010) https://doi.org/10.1117/12.846903

KEYWORDS: Photomasks, Semiconducting wafers, Instrument modeling, Printing, Data modeling, Optical proximity correction, Optical lithography, Bridges, Microelectronics, Manufacturing

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Proceedings Article | 17 October 2008 Paper

Paper

Improving cost of ownership on KLA-Tencor wafer fab reticle inspections by implementing pixel migration via new STARlight2+ capability

Yung-Feng Cheng, Wei-Cyuan Lo, Ming-Jui Chen, Peter Huang, Chunlin Chen, Swapnajit Chakravarty, Paul Yu, Russell Dover

Proceedings Volume 7122, 71223J (2008) https://doi.org/10.1117/12.802331

KEYWORDS: Inspection, Photomasks, Reticles, Semiconducting wafers, Air contamination, Wafer inspection, Metals, Microelectronics, Data processing, Image processing

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Proceedings Article | 19 May 2008 Paper

Paper

Inspectability of PSM masks for the 32nm node using STARlight2+

Chain-Ting Huang, Yung-Feng Cheng, Shih-Ming Kuo, Chun-Hsien Huang, Swapnajit Chakravarty, Joe Huang, Jeff Lin, Den Wang

Proceedings Volume 7028, 70282P (2008) https://doi.org/10.1117/12.793095

KEYWORDS: Inspection, Reticles, Photomasks, Calibration, Reflectivity, Image processing, Contamination, Semiconducting wafers, Lithography, Manufacturing

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Proceedings Article | 25 October 2007 Paper

Paper

Automatic optimization of MEEF-driven defect disposition for contamination inspection challenges

Tracy Huang, Aditya Dayal, Kaustuve Bhattacharyya, Joe Huang, William Chou, Yung-Feng Cheng, Shih-Ming Yen, James Cheng, Peter Peng

Proceedings Volume 6730, 67302B (2007) https://doi.org/10.1117/12.748226

KEYWORDS: Crystals, Reticles, Contamination, Inspection, Quartz, Lithography, Semiconducting wafers, Photomasks, Sensors, Defect detection

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Ever-tightened design rules and ensuing aggressive OPC features pose significant challenges for wafer fabs in the pursuit of compelling yield and productivity. The introduction of advanced reticles considerably augments the mask error enhancement factor (MEEF) where progressive defects or haze, induced by repeated laser exposure, continue to be a source of reticle degradation threatening device yield. High resolution reticle inspection now emerges as a rescue venue for wafer fabs to assure their photomask integrity during intensive deep UV exposure. Integrated in the high resolution reticle inspection, a MEEF-driven lithographic detector "Litho3" can be used run-time to group critical defects into a single bin. Previous investigations evinced that critical defects identified by such detector were directly correlated with defects printed on wafer, upon which fab users can make cogent decisions towards reticle disposition and cleaning therefore reduce cycle time. One of the challenges of implementing such detector resides in the lengthy set up of user-defined parameters, from practitioner standpoint, can considerably extend reticle inspection time and inevitably delay production. To overcome this, an automatic simulation program has been written to optimize Litho3 settings based off a pre-inspection in which only default Litho3 values are needed. Upon completion of the pre-inspection, the images are then scanned and processed to extract the optimal Litho3 parameters that are largely dependent upon the feature size characteristics and local MEEF. Thus optimized Litho3 parameters can then be input into the recipe set up to enable a real-time inspection, as such fab user can timely access the defect criticality information for subsequent defect disposition. In the interest of printability validation, such defect information and associated coordinates can be passed onto defect review via XLINK for further analysis. Corresponding MEEF values are also available for all identified critical defects. Through this automatic program the set up time for Litho3 can be reduced by up to 90%. For high capacity production fabs running a pre-inspection is deemed infeasible; this automatic optimization program can also serve as a direct interpretation of any regular reticle inspection even without invoking Litho3 set up, yet in the end provide output in the context of defect criticality. Results acquired from this program were found in good accordance with those from the real-time Litho3 inspection, for both critical and non-critical layers of 90 nm design node. Such capability allows detailed study of defect criticality in relation to its size, defect optical transmittance, residing surface, its proximity to a printing pattern as well as lithography parameters such as NA and sigma. Furthermore, coupling this automatic program with high resolution inspection also assists in determining lithography process window and an indepth comprehension of defect progression mechanism.

Proceedings Article | 29 May 2007 Paper

Paper

A novel run-time MEEF-driven defect disposition extending high resolution contamination inspection to next generation photomask

William Chou, Yung-Feng Cheng, Shih-Ming Yen, James Cheng, Peter Peng, Joe Huang, Tracy Huang, Den Wang, Ellison Chen, Ching Yun Hsiang, Kaustuve Bhattacharyya, Aditya Dayal

Proceedings Volume 6607, 66072F (2007) https://doi.org/10.1117/12.728998

KEYWORDS: Reticles, Inspection, Semiconducting wafers, Photomasks, Lithography, Defect detection, Sensors, Contamination, Air contamination, Transmittance

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The advent of device miniaturization necessitates sub-half-micron features delineated on reticles where photomask quality, more so than ever, exerts remarkable yield impact on 65 nm node and below. The introduction of advanced reticles considerably augments the mask error enhancement factor (MEEF) in the non-linear regime ensuing aggressive OPC features. The increased MEEF leads to tightened defect capture criteria, in which many of the previously insignificant defects become of interest and may have substantial yield impact. To provide desired sensitivity, a high resolution inspection is a must; it also effectively monitors mask reliability. However, the productivity of such inspection greatly depends on defect disposition efficacy in sorting out critical defects from the large population detected on contaminated masks [1-3]. Anchoring high resolution reticle inspection, wafer fabs are in a relentless pursuit of optimal defect disposition method to meet the throughput demand. In particular, progressive defects or haze, induced by repeated laser exposure, continue to be a source of reticle degradation threatening device yield. Early detection of these defects to circumvent the printability impact becomes vitally important yet challenging. In addition to its size, the defect criticality also largely depends upon defect optical transmittance, residing surface, its proximity to a printing pattern as well as lithography parameters such as NA and sigma [4-6]. A MEEF-driven lithographic detector named "Litho3" has been designed that can be used run-time during mask inspection to effectively group the critical defects into a single bin based on their potential yield impact. The coordinates of these critical defects, identified by the above Litho3 detector, can then be transferred from reticle to wafer and subsequently subject to printability validation, upon which defective sites can be analyzed thoroughly on reticle or wafer review tools. Such capability reduces inspection cycle time by improving defect disposition efficacy, also assists in determining lithography process window and a further comprehension of defect progression mechanism.

Proceedings Article | 15 May 2007 Paper

Paper

Implementation of double dipole lithography for 45-nm node poly and diffusion layer manufacturing with 0.93NA

Meng-Hsiu Wu, Michael Hsu, Stephen Hsu, Bo-Jou Lu, Yung-Feng Cheng, Yueh-Lin Chou, Chuen-Huei Yang

Proceedings Volume 6607, 660731 (2007) https://doi.org/10.1117/12.729020

KEYWORDS: Photomasks, Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Resolution enhancement technologies, Lithography, Manufacturing, Calibration, Data modeling, Printing

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The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography. Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole illumination can help us to reach smaller k1 value (~0.31) and meet the process requirements of poly and diffusion layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the more challenging question should be: how to calibrate a good model from two exposure and decompose original design to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip processing, we need a robust application strategy to ensure a very tight CD control. We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node - X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a process design flow starting from the design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask data preparation. All of the work has been implemented using MaskWeaver^TM geometry engine. Additionally, we investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL process is ready for 45nm node and is well within reach to be used on next generation production environment.

Proceedings Article | 27 March 2007 Paper

Paper

Feasibility Study of 45nm Metal Patterning with 0.93 NA

Yung Feng Cheng, Yueh Lin Chou, Ya Ching Hou, Bo Jou Lu, Chuen Huei Yang

Proceedings Volume 6520, 65204J (2007) https://doi.org/10.1117/12.711367

KEYWORDS: Polarization, Metals, Resolution enhancement technologies, Printing, Semiconducting wafers, Logic, Image processing, Optical lithography, Line width roughness, Image resolution

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Proceedings Article | 26 March 2007 Paper

Paper

Feasibility study of splitting pitch technology on 45-nm contact patterning with 0.93 NA

Yung Feng Cheng, Yueh Lin Chou, Ting Cheng Tseng, Bo Yun Hsueh, Chuen Huei Yang

Proceedings Volume 6520, 65202N (2007) https://doi.org/10.1117/12.711904

KEYWORDS: Printing, Semiconducting wafers, Logic, Optical lithography, Resolution enhancement technologies, Photomasks, Double patterning technology, Etching, Image processing, Atrial fibrillation

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Proceedings Article | 24 March 2006 Paper

Paper

Scatterometry measurements of line end shortening structures for focus-exposure monitoring

Kelvin Hung, Yung Feng Cheng, Jie Wei Sun, Benjamin Szu-Min Lin, Steven Fu, Thaddeus Dziura, Marcelo Cusacovich, Walter Mieher

Proceedings Volume 6152, 61521W (2006) https://doi.org/10.1117/12.655746

KEYWORDS: Single crystal X-ray diffraction, Semiconducting wafers, Data modeling, Scatterometry, Finite element methods, Lithography, Metrology, Process control, Photoresist processing, Scatter measurement

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Proceedings Article | 15 March 2006 Paper

Paper

The investigation of 193nm CPL 3D topology mask effect on wafer process performance

Yung Feng Cheng, Yueh Lin Chou, Chuen Huei Yang

Proceedings Volume 6154, 61542D (2006) https://doi.org/10.1117/12.655165

KEYWORDS: Photomasks, Semiconducting wafers, Quartz, Printing, Critical dimension metrology, 3D metrology, Etching, 3D printing, Atomic force microscopy

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Proceedings Article | 9 November 2005 Paper

Paper

Inspection of integrated circuit database through reticle and wafer simulation: the lithography process window performance monitoring

Bo Su, Gaurav Verma, William Volk, Mohsen Ahmadian, Hong Du, Abhishek Vikram, Scott Andrews, Yung Feng Cheng, Yueh Lin Chou, Chuen Huei Yang, ChinLung Lin

Proceedings Volume 5992, 599244 (2005) https://doi.org/10.1117/12.633010

KEYWORDS: Inspection, Databases, Semiconducting wafers, Reticles, Scanning electron microscopy, Optical proximity correction, Calibration, Defect detection, Bridges, Data modeling

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Proceedings Article | 8 November 2005 Paper

Paper

Study of effects of sidewall angle on process window using 193nm CPL masks in a 300mm wafer manufacturing environment

Yung Feng Cheng, Yueh Lin Chou, C. Lin, Peter Huang

Proceedings Volume 5992, 59922R (2005) https://doi.org/10.1117/12.631079

KEYWORDS: Photomasks, Semiconducting wafers, 3D metrology, 3D printing, Printing, 193nm lithography, Lithography, Wafer manufacturing, Atomic force microscopy

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Proceedings Article | 12 May 2005 Paper

Paper

Feasibility study of sub-65nm contact/hole patterning

Yung Cheng, Te Wu, C. Lin, Sheng Chang, Benjamin Lin

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.599571

KEYWORDS: Lithographic illumination, Optical lithography, Lithography, Logic, Optical proximity correction, Photomasks, Resolution enhancement technologies, Printing, Manufacturing, SRAF

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Showing 5 of 24 publications

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