Dr. Yongjun Wang Profile

Dr. Yongjun Wang

at ASML

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Publications (3)

Proceedings Article | 26 March 2019 Presentation

Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)

Cyrus Tabery, Vito Rutigliani, Simon Hastings, Etienne de Poortere, Luke Wang, Philippe Leray, Guillaume Schelcher, Yongjun Wang

Proceedings Volume 10959, 109591U (2019) https://doi.org/10.1117/12.2516613

KEYWORDS: Overlay metrology, Metrology, Logic, Copper, Inspection, Process modeling, Scanning electron microscopy, Wafer inspection, Error analysis, Photomasks

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Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.

Proceedings Article | 26 March 2019 Presentation + Paper

Investigating process variability at ppm level using advanced massive eBeam CD metrology and contour analysis

B. Le-Gratiet, O. Mermet, C. Gardin, S. Desmoulins, T. Kiers, Y. Wang, P. Tang, D. Tien, F. Wang, C. Prentice, W. Tel, S. Hunsche

Proceedings Volume 10959, 109591A (2019) https://doi.org/10.1117/12.2515242

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Optical lithography, Error analysis, Etching, Scanning electron microscopy, Reliability, Metrology, Control systems, Statistical analysis

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Over the past few years, patterning edge placement error (EPE), which combines information on variability of pattern sizes and placement between adjacent device layers, has been established as the key metric for patterning budget generation and holistic patterning control. More recently, the emergence of high-throughput SEM tools that provide inspection and large-volume CD metrology capabilities has enabled unprecedented statistical analysis of on-product pattern variability.

In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.

To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.

SPIE Journal Paper | 17 August 2018

Assessment of pattern variability and defectivity by large-scale SEM metrology with >100 million measurements

Fuming Wang, Stefan Hunsche, Hung Yu Tien, Peng Tang, Junwei Wei, Yongjun Wang, Wei Fang, Patrick Wong

JM3, Vol. 17, Issue 04, 041007, (August 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041007

KEYWORDS: Semiconducting wafers, Scanning electron microscopy, Stochastic processes, Critical dimension metrology, Metrology, Photomasks, Inspection, Optical proximity correction, Electron beam lithography, Etching

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