Mr. Vito Daniele Rutigliani Profile

Vito Daniele Rutigliani

Process Metrology Eng at ASML

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Author

Publications (13)

Proceedings Article | 26 March 2019 Presentation + Paper

Roughness decomposition: an on-wafer methodology to discriminate mask, metrology, and shot noise contributions

Gian Francesco Lorusso, Gijsbert Rispens, Vito Rutigliani, Frieda Van Roey, Andreas Frommhold, Guido Schiffelers

Proceedings Volume 10959, 109590T (2019) https://doi.org/10.1117/12.2515175

KEYWORDS: Photomasks, Line width roughness, Semiconducting wafers, Metrology, Stochastic processes, Scanning electron microscopy, Critical dimension metrology, Data modeling, Linear filtering, Extreme ultraviolet lithography

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In order to meet the tight Line Width Roughness (LWR) requirements for advanced metrology nodes, it is critical to be able to identify what the fundamental sources of roughness are, so that they can be individually minimized. In fact, more and more efforts aiming to decouple mask and / or metrology contribution from wafer data have been recently reported [1]. However, these approaches often rely heavily on extensive mask characterization, something that is not always easily available.

We propose here an alternative path to investigate and discriminate the root causes of LWR using only wafer data. It is based on Local Critical Dimension Uniformity (LCDU) decomposition [2], a methodology used to identify and quantify the individual LCDU contributors. The decomposition approach requires a smart sampling of the wafer print, in which an array of contact hole is measured in different dies multiple times. For such an approach to be successful, it is critical to ensure that the measurement locations are individually identified. Hence, it is necessary to anchor the metrology to a reference feature. A linear nested model [3] is then used to quantify the three main variability components (mask, shot noise, and metrology). This approach allows to sample thousands of features at mask, a task that would not be practically achievable through direct mask measurements.

In this work, LWR decomposition is implemented for the first time. To this aim, 18nm lines at 36nm pitch, printed by EUV lithography, were used. We specifically worked with a pattern including programmed defects, used as anchoring features for the metrology. In order to limit the impact of the metrology noise, expected to be higher for lines as compared to CH, we sampled over 8000 anchored measurements per image (in the CH case, only 81 measurements per image were needed). The LWR decomposition results indicated the dominance of the metrology noise, as expected. In addition, the mask contribution was observed to be less relevant that the shot noise.

To verify the accuracy of the LWR decomposition results, Power Spectral Density (PSD) analysis on wafer and mask SEM images was used. The metrology noise contribution was removed at both mask and wafer level using an un-biasing normalization of the PSD curves [4]. The comparison with the PSD analysis confirmed the feasibility of LWR decomposition, opening the way to a more effective diagnostic technique for roughness and stochastics.

Proceedings Article | 26 March 2019 Presentation + Paper

Deep learning nanometrology of line edge roughness

Eva Giannatou, Vassilios Constantoudis, George Papavieros, Harria Papagrorgiou, Gian Francesco Lorusso, Vito Rutigliani, Frieda van Roey, Evangelos Gogolides

Proceedings Volume 10959, 1095920 (2019) https://doi.org/10.1117/12.2520941

KEYWORDS: Line edge roughness, Scanning electron microscopy, Denoising, Signal to noise ratio, Image processing, Data modeling, Image denoising, Edge detection, Interference (communication), Image filtering

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Proceedings Article | 26 March 2019 Presentation

Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)

Cyrus Tabery, Vito Rutigliani, Simon Hastings, Etienne de Poortere, Luke Wang, Philippe Leray, Guillaume Schelcher, Yongjun Wang

Proceedings Volume 10959, 109591U (2019) https://doi.org/10.1117/12.2516613

KEYWORDS: Overlay metrology, Metrology, Logic, Copper, Inspection, Process modeling, Scanning electron microscopy, Wafer inspection, Error analysis, Photomasks

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Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.

SPIE Journal Paper | 10 November 2018

Setting up a proper power spectral density and autocorrelation analysis for material and process characterization

Vito Rutigliani, Gian Francesco Lorusso, Danilo De Simone, Frederic Lazzarino, George Papavieros, Evangelos Gogolides, Vassilios Constantoudis, Chris A. Mack

JM3, Vol. 17, Issue 04, 041016, (November 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041016

KEYWORDS: Scanning electron microscopy, Line edge roughness, Materials processing, Extreme ultraviolet, Line width roughness, Etching, Lithography, Image filtering, Material characterization, Image acquisition

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SPIE Journal Paper | 13 October 2018

Line edge roughness metrology: recent challenges and advances toward more complete and accurate measurements

Vassilios Constantoudis, George Papavieros, Gian Lorusso, Vito Rutigliani, Frieda Van Roey, Evangelos Gogolides

JM3, Vol. 17, Issue 04, 041014, (October 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041014

KEYWORDS: Line edge roughness, Scanning electron microscopy, Fractal analysis, Metrology, Edge roughness, Etching, Lithography, Image processing, Optical lithography, Image segmentation

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SPIE Journal Paper | 12 September 2018

Need for LWR metrology standardization: the imec roughness protocol

Gian Francesco Lorusso, Takumichi Sutani, Vito Rutigliani, Frieda van Roey, Alain Moussa, Anne-Laure Charley, Chris Mack, Patrick Naulleau, Chami Perera, Vassilios Constantoudis, Masami Ikota, Toru Ishimoto, Shunsuke Koshihara

JM3, Vol. 17, Issue 04, 041009, (September 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041009

KEYWORDS: Metrology, Line width roughness, Scanning electron microscopy, Digital filtering, Atomic force microscopy, Standards development, Semiconductors, Image acquisition, Image quality, Electron microscopes

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As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: line width roughness (LWR) specifications are expected to be <2 nm in the near term, and to drop below 1 nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. We report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines [such as measurement box length >2 μm and the need to correct for scanning electron microscope (SEM) noise]. We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol—the imec roughness protocol—intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such as LWR, everyone speaks the same language, which is not currently the case.

Proceedings Article | 30 March 2018 Presentation + Paper

Setting up a proper power spectral density (PSD) and autocorrelation analysis for material and process characterization

Vito Rutigliani, Gian Francesco Lorusso, Danilo De Simone, Frederic Lazzarino, Gijsbert Rispens , George Papavieros, Evangelos Gogolides, Vassilios Constantoudis, Chris Mack

Proceedings Volume 10585, 105851K (2018) https://doi.org/10.1117/12.2297264

KEYWORDS: Materials processing, Line width roughness, Image filtering, Line edge roughness, Material characterization, Image acquisition, Image processing, Scanning electron microscopy, Extreme ultraviolet, Double patterning technology

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Proceedings Article | 28 March 2018 Presentation + Paper

The need for LWR metrology standardization: the imec roughness protocol

Gian Francesco Lorusso, Takumichi Sutani , Vito Rutigliani, Frieda van Roey, Alain Moussa, Anne-Laure Charley, Chris Mack, Patrick Naulleau, Vassilios Constantoudis , Masami Ikota , Toru Ishimoto, Shunsuke Koshihara

Proceedings Volume 10585, 105850D (2018) https://doi.org/10.1117/12.2294617

KEYWORDS: Line width roughness, Metrology, Standards development, Semiconductors, Scanning electron microscopy, Image acquisition, Atomic force microscopy, Finite element methods, Semiconducting wafers, Time metrology

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As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Proceedings Article | 20 March 2018 Paper

Ultimate edge-placement control using combined etch and lithography patterning optimizations

Brennan Peterson, Rich Wise, Koen van der Straten, Katja Viantka, Melisa Luca, Salman Mokhlespour, Michael Kubis, Giordano Cattani, David Hellin, Daniel Sobieski, Girish Dixit, Nader Shamma, Vito Rutigliani, Patrick Jaenen, Sandip Halder, Philippe Leray

Proceedings Volume 10586, 105860A (2018) https://doi.org/10.1117/12.2297401

KEYWORDS: Etching, Critical dimension metrology, Line width roughness, Lithography, Line edge roughness, Stochastic processes, Semiconducting wafers, Optical lithography, Photomasks, Extreme ultraviolet

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Proceedings Article | 20 March 2018 Paper

Computational nanometrology of line-edge roughness: noise effects, cross-line correlations and the role of etch transfer

Vassilios Constantoudis, George Papavieros, Gian Lorusso, Vito Rutigliani, Frieda Van Roey, Evangelos Gogolides

Proceedings Volume 10589, 105890Y (2018) https://doi.org/10.1117/12.2306282

KEYWORDS: Line edge roughness, Etching, Scanning electron microscopy, Metrology, Lithography, Edge roughness, Image processing, Optical lithography, Image analysis, Statistical analysis

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The aim of this paper is to investigate the role of etch transfer in two challenges of LER metrology raised by recent evolutions in lithography: the effects of SEM noise and the cross-line and edge correlations.

The first comes from the ongoing scaling down of linewidths, which dictates SEM imaging with less scanning frames to reduce specimen damage and hence with more noise. During the last decade, it has been shown that image noise can be an important budget of the measured LER while systematically affects and alter the PSD curve of LER at high frequencies. A recent method for unbiased LER measurement is based on the systematic Fourier or correlation analysis to decompose the effects of noise from true LER (Fourier-Correlation filtering method). The success of the method depends on the PSD and HHCF curve. Previous experimental and model works have revealed that etch transfer affects the PSD of LER reducing its high frequency values. In this work, we estimate the noise contribution to the biased LER through PSD flat floor at high frequencies and relate it with the differences between the PSDs of lithography and etched LER. Based on this comparison, we propose an improvement of the PSD/HHCF-based method for noise-free LER measurement to include the missed high frequency real LER.

The second issue is related with the increased density of lithographic patterns and the special characteristics of DSA and MP lithography patterns exhibits. In a previous work, we presented an enlarged LER characterization methodology for such patterns, which includes updated versions of the old metrics along with new metrics defined and developed to capture cross-edge and cross-line correlations. The fundamental concept has been the Line Center Roughness (LCR), the edge c-factor and the line c-factor correlation function and length quantifying the line fluctuations and the extent of cross-edge and cross-line correlations. In this work, we focus on the role of etch steps on cross-edge and line correlation metrics in SAQP data. We find that the spacer etch steps reduce edge correlations while etch steps with pattern transfer increase these. Furthermore, the density doubling and quadrupling increase edge correlations as well as cross-line correlations.

Proceedings Article | 19 March 2018 Presentation + Paper

EUV photoresist patterning characterization for imec N7/N5 technology

Danilo De Simone, Vito Rutigliani, Gian Lorusso, Peter De Bisschop, Yannick Vesters, Victor Blanco Carballo, Geert Vandenberghe

Proceedings Volume 10583, 105830G (2018) https://doi.org/10.1117/12.2299504

KEYWORDS: Optical lithography, Scanning electron microscopy, Extreme ultraviolet lithography, Lithography, Critical dimension metrology, Photoresist materials, Extreme ultraviolet, Line edge roughness, Metrology, Line width roughness

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In the last year, the continuous efforts on the development of extreme ultraviolet (EUV) lithography has allowed to push the lithographic performance of the EUV photoresists on the ASML NXE:3300 full field exposure tool. Today imec N7 node (equivalent to foundry N5) is the first scaling node at which industry will likely insert EUV into production which will bring a reduction in processing steps therefore reducing total cost of ownership [1], increasing yield and reducing time to ramp. However, the high-volume-manufacturing (HVM) requirement to have a cost-effective low exposure dose photoresist (<20mJ/cm²) remains a big challenge and roughness and pattern defectivity at nano-scale are the major limiting factors of the lithographic process window of EUV resist when looking at tight pitches below 40nm [2, 3].

To be effective during the lithographic EUV material screening phase for such tight pitches, it is necessary to implement complementary metrology analyses that can provide precise information on the resist roughness and a quick feedback on the quantification of nano-failures (nano-bridges, broken lines, merging or missing contacts) induced by a stochastic EUV patterning regime, the random nature of the light-matter interaction and consequent chemical reactions. Beside the traditional approach to characterize a resist with metrics as exposure latitude (EL%), depth of focus (DoF) and line-edge-roughness (LER) based on CDSEM measurements, we have used the power spectra density (PSD) [4] to get an unbiased value of the resist line roughness (LWR and LER) by using Fractilia metroLER^TM commercial software. Further, we have used Stochalis imec software [5] to quantify patterning nano failures providing an early stage assessment on the patterning fidelity of the examined resists.

We present the resist characterization results for 32nm dense line-space pattern on different substrates and for 36nm dense and orthogonal contact hole pitch pattern for different photoresists. Two positive tone chemically amplified (CA) resists have been identified at the exposure dose of 45mJ/cm² and 33mJ/cm² for logic (pitch 32nm dense line/space) and memory (pitch 36nm dense contact holes) use cases, respectively.

Proceedings Article | 13 March 2018 Paper

Multifractal analysis of line-edge roughness

Vassilios Constantoudis, George Papavieros, Gian Lorusso, Vito Rutigliani, Frieda van Roey, Evangelos Gogolides

Proceedings Volume 10585, 1058534 (2018) https://doi.org/10.1117/12.2306508

KEYWORDS: Line edge roughness, Fractal analysis, Scanning electron microscopy, Lithography, Etching, Image processing, Image segmentation, Edge roughness, Optical lithography, Metrology

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In this paper, we propose to rethink the issue of LER characterization on the basis of the fundamental concept of symmetries. In LER one can apply two kinds of symmetries: a) the translation symmetry characterized by periodicity and b) the scaling symmetry quantified by the fractal dimension. Up to now, a lot of work has been done on the first symmetry since the Power Spectral Density (PSD), which has been extensively studied recently, is a decomposition of LER signal into periodic edges and quantification of the ‘power’ of each periodicity at the real LER. The aim of this paper is to focus on the second symmetry of scaling invariance. Similarly to PSD, we introduce the multifractal approach in LER analysis which generalizes the scaling analysis of standard (mono)fractal theory and decomposes LER into fractal edges characterized by specific fractal dimensions. The main benefit of multifractal analysis is that it enables the characterization of the multi-scaling contributions of different mechanisms involved in LER formation. In the first part of our work, we present concisely the multifractal theory of line edges and utilize the Box Counting method for its implementation and the extraction of the multifractal spectrum. Special emphasis is given on the explanation of the physical meaning of the obtained multifractal spectrum whose asymmetry quantifies the degree of multifractality. In addition, we propose the distinction between peak-based and valley-based multifractality according to whether the asymmetry of the multifractal spectrum is coming from the sharp line material peaks to space regions or from the cavities of line materis (edge valleys). In the second part, we study systematically the evolution of LER multifractal spectrum during the first successive steps of a multiple (quadruple) patterning lithography technique and find an interesting transition from a peak-based multifractal behavior in the first litho resist LER to a valley-based multifractality caused mainly by the effects of etch pattern transfer steps.

Proceedings Article | 27 March 2017 Presentation + Paper

Exploration of a low-temperature PEALD technology to trim and smooth 193i photoresist

Frederic Lazzarino, Sara Paolillo, Anthony Peter, David De Roest, TaeGeun Seong, Yizhi Wu, Stefan Decoster, Vito Rutigliani, Gian Francesco Lorusso, Vassilios Constantoudis, Sven Van Elshocht, Daniele Piumi, Kathy Barla

Proceedings Volume 10146, 101460K (2017) https://doi.org/10.1117/12.2258040

KEYWORDS: Optical lithography, Extreme ultraviolet lithography, Photoresist materials, Metals, Extreme ultraviolet, Double patterning technology, Back end of line, Semiconductors, High volume manufacturing, Line edge roughness, Chemistry, Argon, Plasma, Semiconducting wafers, Surface roughness, Line width roughness, FT-IR spectroscopy

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