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The microelectronics industry faces constant challenges in improving the quality and performance of electronic circuits, especially when addressing markets with high reliability requirements. One of the main challenges is to improve robustness of our technologies, making a rapid diagnosis of any parametric signature observed.
This paper describes the added value of using a massive e-beam inspection tool combined with CD SEM and contour analysis to accelerate the diagnostic of a process from a variability point of view. Massive CD and contour-based measurement have been used to investigate recurrent but nonsystematic signatures related to Poly Contact shorts risks.
Control plan definition for Critical Dimension (CD) and Overlay (OVL) is set up by performing CD and OVL windowing (modulated wafers in dose for CD and Translation or Scaling for OVL that are sent to yield). The variations are set so that yield failures are reached across the window. These wafers are typically densely measured on reference CD and OVL targets (dedicated metrology structures). The correlation of those measurements to yield leads to in-line specification limits and sampling definition. However, the statistical level of metrology information is not at the same level of yield EWS (Electrical Wafer Sorting) where all dies are measured. Massive e-beam Inspection changes the paradigm by enabling the measurement of every die on the wafer in a reasonable time and better anticipate probability of potential yield excursions.
Poly Contact shorts, is a situation caused by a contact edge getting too close to the gate edge. Process robustness consolidation can be particularly challenging due to the multiple sources of variability in the fabrication process, especially in the patterning process (photolithography and etching process). One of the very first actions in such situations is to perform a process variability breakdown: global (lot to lot, wafer to wafer, intra wafer, intra field) and local (LCDU and PCDU). From previous work it is also known that for critical lithography steps local components happen to be the largest contributors.
In this paper, massive ebeam technology is being used to characterize intra wafer and intra field component for CD and Overlay at die level (with the same spatial resolution as yield EWS map) while contour-based metrology from in-line CDSEM images gives complementary insight on local variability. Combining such “metrology” resources can be called metro-spection approach. This enables more exhaustive variability breakdown and time to decision and qualification is being accelerated. Finally, it will be shown that deploying a new process reducing local pattern CD variability is the most effective solution to increase robustness.
Modern Integrated Circuits (IC) manufacturing consists of a complex series of process steps and each transition to smaller semiconductor technology nodes has come with a significant increase in the number of steps. Apart from this increased technological complexity, also the cost of semiconductor manufacturing has risen significantly. A high yield is therefore of utmost importance to ensure the overall profitability of the modern IC manufacturing process, meaning that each process step needs to be executed flawlessly, in particular due to accumulative nature of yield loss.
Photolithography is one of the many process steps in IC manufacturing that is executed repeatedly and overlay is one of its most critical parameters. Maintaining good overlay performance is thus key for maximizing yield and guaranteeing the overall profitability of the IC production process. Overlay metrology plays an important role in keeping this good performance in high-volume manufacturing (HVM), and the measurements are used as input for the Advanced Process Control (APC) system as well as for lot dispositioning. Preferably, the amount of metrology is reduced to a bare minimum to reduce cost and decrease fab cycle time, and overlay is typically measured on only a fraction of the wafers. In case metrology reduction is going too far, then there is a risk that bad wafers and/or lots pass, resulting in potential yield loss or even wafer scrap, which will increase the cost again. The challenge is to find the sweet spot for using the available metrology in the most efficient way.
Virtual metrology is a solution that aims to enable metrology coverage for every single wafer, and with that applications like smarter sampling with the goal of using metrology more efficiently. Basically, virtual metrology is the use of algorithms to predict wafer properties like overlay based on previous metrology measurements and/or processing equipment sensor data. In previous work, we developed virtual metrology, or computational overlay, based on a hybrid approach that combines domain knowledge-based physical modeling with machine learning. A good prediction performance was demonstrated on the critical overlay between contact and gate layers that were exposed with chuck dedication. Furthermore, we also showed that computational overlay could be used to reduce the field magnification errors that were observed in the lot-to-lot variation.
In this paper, we build upon our earlier work and extend the applicability of the computational overlay model towards layers that are exposed without chuck dedication, or even on different scanners. We will assess the prediction performance on a few Via layers in the back-end-of-line. Furthermore, as the model is able to predict the overlay for all wafers in the lot, we will demonstrate its capability of detecting an intermittent first wafer effect on one particular lithography cluster that was causing non-optimal quality.
This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox.
Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.
In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.
To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.
Process windows are getting tight with a greater and greater contribution of the focus budget. Nanotopography is highly correlated to the chip layout. As a consequence it shows systematic peaks and valleys shifting locally optimum process conditions. Mean, standard deviations and ranges are not enough to characterize it.
It is of high importance to know topography maps to identify care areas on silicon with high risks of defocus situations [2]. These maps can be measured at any process step using PWG (Patterned Wafer Geometry) tools but could also be predicted with models (see proof of concept [3]).
The first part of this paper deals with the development of scripts to extract and express in multiples ways topography information. Different types of expressions will be shown followed by two use cases related to topography description situation: striation detection and slurry choice for CMP. Those two use cases are proofs of concepts showing that data valorization is a path to provide information that can help process engineers to make decisions and save time for defect detection.
This paper ends with a deeper exploration of the correlations between chip designs and nanotopography from an image processing point of view (design layout and wafer topography maps). Short-range and long-range contributions of layouts are used to model nano-topography through a multiple linear regression [4] of the pre-processed design layers densities (surface and perimeter) and wafer topography which is characterized in this work using KLA PWG tooling. The goal being here to predict wafer topography before silicon is being processed so that mitigation solutions can be set up.
PWG metrology tool can measure a full wafer nano-topography map with pixels size of 100μm*100μm which is enough for a focus analysis. Results show that the first model version reaches encouraging figures of 0.77 R2 for a product layer having a 20nm topography range.
This sampling tool can use different inputs (production, tools, APC…) in a dynamic way. This means that the system is dynamic for both process and metrology aspects, and can be adapted to integrate different variables and external events. A real time communication flow was created between APC and sampling tool. Even if the measurement skip decision is taken by the sampling tool, the APC feedback is systematically requested when run to run is involved, like for all lithography process steps. The strength is to deal with high products / mix complexity and react in real time to new product introduction, process deviation, atypical lots including R&D projects and sudden change of the products mix. Both tools are so linked that the sampler remains invisible. Process engineers continue to manage and control lithography process through APC tool mainly.
In parallel, different alarms and triggers have been implemented, including a specific “crisis” mode to quickly respond to the metrology equipment loading or availability variability.
The sampler introduction allowed an optimization of the metrology toolset costs and lot cycle time improvement. Also as a consequence, a more efficient metrology control plan, with an optimized balance between process criticality and metrology requirements.
Future opportunities are related to more dynamic behaviors, as a dynamic sampling rate adapted to metrology capacity, function of the real time metrology capacity or sampling decision dynamically based on process variability components.
Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product.
The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.
This work will show that chip topography can be predicted from reticle density and perimeter density data, including experimental proof. Different pixel sizes are used to perform the correlation in-line with the minimum resolution, correlation length of CMP effects and the spot size of the scanner level sensor. Potential applications of the topography determination will be evaluated, including optimizing scanner leveling by ignoring non-critical parts of the field, and without the need for time-consuming offline topography measurements.
The introduction of pitch splitting (Litho-Etch-Litho-Etch) at 14FDSOInm node requires the development of specific metrologies to adopt advanced process control (for CD, overlay and focus corrections). The pitch splitting process leads to final line CD uniformities that are a combination of the CD uniformities of the two exposures, while the space CD uniformities are depending on both CD and OVL variability.
In this paper, investigations of CD and OVL process control of 64nm minimum pitch at Metal1 level of 14FDSOI technology, within the double patterning process flow (Litho, hard mask etch, line etch) are presented.
Various measurements with SEMCD tools (Hitachi), and overlay tools (KT for Image Based Overlay – IBO, and ASML for Diffraction Based Overlay – DBO) are compared. Metrology targets are embedded within a block instanced several times within the field to perform intra-field process variations characterizations.
Specific SEMCD targets were designed for independent measurement of both line CD (A and B) and space CD (A to B and B to A) for each exposure within a single measurement during the DP flow.
Based on those measurements correlation between overlay determined with SEMCD and with standard overlay tools can be evaluated.
Such correlation at different steps through the DP flow is investigated regarding the metrology type. Process correction models are evaluated with respect to the measurement type and the intra-field sampling.
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