KEYWORDS: Optical lithography, Extreme ultraviolet lithography, Stochastic processes, Photoresist processing, Metrology, Metals, Lithography, Back end of line
An all-EUV dry resist technology offers a fundamentally new way to enable resist processing targeting differentiating capabilities for high NA lithography. Dry deposition of resists offers stochastic benefits with precise control over thickness and composition. Dry development enables in-situ tuning of development and also improves pattern collapse margin for higher aspect ratios. In this talk, we establish the progress of dry resist development toward extending the limits of single expose with 0.33NA EUV lithography. We assess electrical yield performance with a BEOL Cu-dual damascene test vehicle at aggressive 28nm and 26nm single expose metal pitches and correlate with defect metrology. We also present improvements in 26/28nm pitch line/space patterning and sub-40nm pitch contact hole patterning by optimization of process parameters such as underlayer, bake, dry development and pattern transfer.
Transistor architectures below the 7 nm node are significantly enabled by EUV lithography, with single exposure EUV processes simplifying small pitch patterning processes. However, EUV stochastics are a significant hurdle in meeting aggressive process assumption targets and achieving high yields. In particular, line edge roughness and line width roughness (LER and LWR) at EUV patterned gate have been identified as key limiters of device performance and yield within these nodes. Here, we study the impact of different illumination schemes on gate LER and LWR. We specifically utilize NILS to target LER and LWR reduction, with high NILS observed to primarily reduce high frequency roughness. Post etch, a largely illumination independent reduction in the mid and high frequency regimes is observed. Finally, impact of illumination on long channel gate patterning is assessed and a NILS independent LWR response is observed both post development and etch.
As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at lithography and etch process and eliminate film-related defects. These approaches require improvements to the process chemicals and the lithography process equipment to achieve finer patterns. ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) technique has been developed and optimized to fulfil this novel development need. ESPERTTM has demonstrated a capability that can enhance the developing contrast between the EUV exposed and unexposed areas. This paper reviews 23 nm pitch line and space and sub-40 nm pitch pillars which were realized by optimized illuminators with 0.33 NA single exposure, and we will show how ESPERTTM helped improve the minimum critical dimension size, defectivity, roughness and electrical yield at the finer patterns.
As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness after lithography and etch processes and eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. The ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) technique has been developed and optimized to fulfil this novel development need. The ESPERTTM has demonstrated a capability that can enhance the developing contrast between the EUV exposed and unexposed areas. This paper reviews that 23 nm pitch line and space and sub-40 nm pitch pillars patterns were realized by high NILS illuminations with 0.33 NA single exposure, and we will show the ESPERTTM helped reduce the minimum critical dimension size, defectivity and roughness at the finer patterns.
As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at lithography and etching and eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns [1]. This paper reviews the ongoing progress in coater/developer processes to enable EUV patterning with sub-30 nm line and space and sub-40 nm pillars by using metal oxide resist (MOR). We show that combining new material with optimized illumination and processes helped reduce the minimum critical dimension size, defectivity, and roughness
Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.
IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.
Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of GAA devices requires new specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology continues through research and development cycles and looks to transition to manufacturing, there are many opportunities and challenges remaining for inline metrology. Especially valuable are measurement techniques which are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact to the frequency of cycles of learning. More than previous nodes, then, this node may be when some of these offline techniques jump from the lab to the fab, as certain critical measurements need to be monitored realtime. Thanks to the compute revolution this very industry enabled, machine learning has begun to permeate inline disposition, and hybrid metrology systems continue to advance. Metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness (LER), pitchwalk, and defectivity continue to be managed. This paper reviews related prior studies and advocates for future metrology development that ensures nanosheet technology has the inline data necessary for success.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.
The ability to etch silicon highly anistropically at active fin heights of 45nm or greater is critical to fin patterning for continued CMOS scaling. Tight control of fin CD and taper is critical toward controlling the device, with particular importance to channel control. In this study we explore the quasi-atomic layer etch (qALE) parameter space in order to better understand the impact of plasma conditions on fin CD, profile, and aspect ratio dependent etch phenomena. A qALE solution is needed to provide a manufacturable solution for a vertical square bottom fin.
In this study a cyclic chlorination (surface modification) + ion bombardment process (modified surface removal) is used to etch Si with a Si3N4 hard mask. Various parameters are explored including bias power, pressure, and time in the ion bombardment step as well as source power, pressure, and time in the chlorination step. With regards to the ion bombardment step, varying time helps to quantify the self-limitation of the etch process, modulating pressure helps to quantify the impact of reduced mean free path and ion density, and modifying source power helps to quantify the impact of changes to ion density. For the chlorination step, varying time helps to quantify the self-limitation of surface modification mechanism, and modifying source power illustrates the impact of Cl radical density on surface modification. These various mechanisms will be explored with the particular view point of how these changes can impact ultimate channel performance.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.
Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask has to scale accordingly. We have reported a grafted polymer brush adhesion layer used in an ultrathin EUV patterning stack and demonstrated sub-36 nm pitch features with significant improvement over existing adhesion promotion techniques [1]. This paper provides further understanding of this class of materials from a fundamental point of view. We first propose a hypothesis of the adhesion mechanism, and probe key factors that could affect adhesion performance. The grafting kinetics study of polymer brush that contains different functional groups to the substrate shows grafting chemistry, time, and temperature are key factors that affect the printing performance. We then conduct a systematic study to understand printing capability at various pitches for different silicon-based substrates. By comparing the process window, we gain comprehensive understanding of the printing limits and failing modes with this approach. We provide a comparative study of a grafted adhesion layer vs. a conventional spin on BARC type material, including defectivity. Pattern transfer to hard mask with varied etch chemistry is conducted to understand the performance of polymer brush during etch.
Extending extreme ultraviolet (EUV) single exposure patterning to its limits requires more than photoresist development. The hardmask film is a key contributor in the patterning stack that offers opportunities to enhance lithographic process window, increase pattern transfer efficiency, and decrease defectivity when utilizing very thin film stacks. This paper introduces the development of amorphous silicon (a-Si) deposited through physical vapor deposited (PVD) as an alternative to a silicon ARC (SiARC) or silicon-oxide-type EUV hardmasks in a typical trilayer patterning scheme. PVD offers benefits such as lower deposition temperature, and higher purity, compared to conventional chemical vapor deposition (CVD) techniques. In this work, sub-36nm pitch line-space features were resolved with a positive-tone organic chemically-amplified resist directly patterned on PVD a-Si, without an adhesion promotion layer and without pattern collapse. Pattern transfer into the underlying hardmask stack was demonstrated, allowing an evaluation of patterning metrics related to resolution, pattern transfer fidelity, and film defectivity for PVD a-Si compared to a conventional tri-layer patterning scheme. Etch selectivity and the scalability of PVD a-Si to reduce the aspect ratio of the patterning stack will also be discussed.
Initial readiness of extreme ultraviolet (EUV) patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the “effective” k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Using a grafted polymer brush adhesion layer, we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush, and resist. We show printing of sub-36-nm pitch features with a good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight, and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
With the increasing prevalence of complex device integration schemes, trilayer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination and are limited in their ability to scale down thickness without compromising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of plasma-enhanced atomic layer deposited (PEALD) TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a trilayer scheme patterned with PEALD-based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited versus a spin-on metal hardmask.
Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.
The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.
With the increasing prevalence of complex device integration schemes, tri layer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination, and are limited in their ability to scale down thickness without comprising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of PEALD deposited TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a tri layer scheme patterned with PEALD based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited vs a spin-on metal hardmask.
High resolution Extreme Ultraviolet (EUV) patterning is currently limited by EUV resist thickness and pattern collapse, thus impacting the faithful image transfer into the underlying stack. Such limitation requires the investigation of improved hardmasks (HMs) as etch transfer layers for EUV patterning. Ultrathin (<5nm) inorganic HMs can provide higher etch selectivity, lower post-etch LWR, decreased defectivity and wet strippability compared to spin-on hybrid HMs (e.g., SiARC), however such novel layers can induce resist adhesion failure and resist residue. Therefore, a fundamental understanding of EUV resist-inorganic HM interactions is needed in order to optimize the EUV resist interfacial behavior. In this paper, novel materials and processing techniques are introduced to characterize and improve the EUV resist-inorganic HM interface. HM surface interactions with specific EUV resist components are evaluated for open-source experimental resist formulations dissected into its individual additives using EUV contrast curves as an effective characterization method to determine post-development residue formation. Separately, an alternative adhesion promoter platform specifically tailored for a selected ultrathin inorganic HM based on amorphous silicon (aSi) is presented and the mitigation of resist delamination is exemplified for the cases of positive-tone and negative-tone development (PTD, NTD). Additionally, original wafer priming hardware for the deposition of such novel adhesion promoters is unveiled. The lessons learned in this work can be directly applied to the engineering of EUV resist materials and processes specifically designed to work on such novel HMs.
Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.
Initial readiness of EUV patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Here, using a grafted polymer brush adhesion layer we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush and resist. We show printing of sub-36 nm pitch features with good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
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